Hipex-RC provides an accurate and fast solution for the extraction of parasitic capacitance and resistance from hierarchical layouts of analog, mixed-signal, memory IC and SoC designs. Working from GDSII, cell netlists and rule-based technology files, Hipex-RC performs the parasitic extraction for either the full chip or selected nets or nodes, then back-annotates the schematic netlist with the exacted parasitics. The device extraction capabilities of Hipex-RC allows the generation of hierarchical netlists that preserve the original layout hierarchy and supports a wide range of standard and parameterized user-defined devices.
In addition it performs electrical rule checking ERC for shorts, opens and dangles. Built for efficient parallelization on multi-processing servers, Hipex-RC is fast with efficient memory usage for large, full chip designs. Hipex-FS is driven via the Silvaco Expert layout tool, for an designer-friendly 3D field solution based RC extraction, utilizing the same physics and solvers as Clever.
Clever is a TCAD-like script based solution, and is ideal for detailed extraction of cell layouts and is a physics-based resistance and capacitance field solver for any arbitrary 3D shaped structure. Both Clever and Hipex-FS performs RC extraction with the highest accuracy, productivity and versatility for the most complicated interconnect cells, including realistic etching and deposition processes. The local adaptive-mesh refinement AMR feature allows the user to specify a desired accuracy.
It will automatically refine the unstructured mesh where required, optimizing maximum accuracy, together with minimum simulation time. We may request cookies to be set on your device. Its seamless integration with Zeni Veri makes it possible to directly generate a netlist file containing parasitic parameters from GDSII layout data.
Only the process parameters and extraction commands are necessary in command files; there is no need to include sophisticated equations or formulas. The parasitic extraction results are marked at the corresponding places on the layout to facilitate the searching of nodes and devices. It also support interactive extraction of RC parasitic elements for nets selected in Zeni PDT, and the result will be passed to Zeni SI for interconnect timing analysis, noise analysis and RC reduction.
This is useful for the parasitic resistor extraction since parasitic resistor extraction will change the nodes in the original layout. The relationship between the original circuit nodes and the extracted circuit nodes can be easily traced along with devices and nodes both in original layout and schematic views.
Parasitic Resistor Extraction Since parasitic resistor elements only depend on the shape of the layout geometries and the layer conductance, it is easier to calculate the parasitic resistor elements than it is to calculate the parasitic capacitor and parasitic inductor elements.
Zeni PE can calculate the parasitic resistor elements with two levels of precision, with the higher precision setting taking longer runtime. Parasitic Capacitor Extraction Quasi-3D parasitic extraction sweeps any 3-D structure in multiple passes and includes geometry superposition.
Working from GDSII, cell netlists and rule-based technology files, Hipex-RC performs the parasitic extraction for either the full chip or selected nets or nodes, then back-annotates the schematic netlist with the extracted parasitics.
The device extraction capabilities of Hipex-RC allows the generation of hierarchical netlists that preserve the original layout hierarchy and supports a wide range of standard and parameterized user-defined devices. In addition it performs electrical rule checking ERC for shorts, opens and dangles.
Built for efficient parallelization on multi-processing servers, Hipex-RC is fast with efficient memory usage for large, full chip designs. We may request cookies to be set on your device. We use cookies to let us know when you visit our websites, how you interact with us, to enrich your user experience, and to customize your relationship with our website.
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